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HT86XXX Voice Synthesizer 8-Bit MCU
Features
* Operating voltage: 2.4V~5.2V * System clock: 4MHz~8MHz * Crystal or RC oscillator for system clock * 23 I/O pins with 4 shared pins included * 8K16-bit program ROM * 2088-bit RAM * One external interrupt input * Three 16-bit programmable timer counter and over* Watchdog Timer * 8-level subroutine nesting * HALT function and wake-up feature reduce power
consumption
* Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)
system clock
* Support 16-bit table read instruction (TBLP, TBHP) * 63 powerful and efficient instructions * HT86072/144/192/384: 28-pin SOP, 100-pin QFP
flow interrupts * 12-bit high quality D/A output by transistor or HT82V733
* Built-in voice ROM in various capacity * One optional 32768Hz crystal oscillator for RTC time
package
* HT86576/768: 32-pin SOP, 100-pin QFP package
base (8-bit counter with 3-bit prescaler)
Applications
* Intelligent educational leisure products * Alert and warning systems * High end leisure product controllers * Sound effect generators
General Description
The HT86XXX series are 8-bit high performance microcontroller with voice synthesizer and tone generator. The HT86XXX is designed for applications on multiple I/Os with sound effects, such as voice and melody. It can provide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator. It has a single built-in high quality, D/A output. There is an external interrupt which can be triggered with falling edge pulse or falling/rising edge pulse. The HT86XXX is excellent for versatile voice and sound effect product applications. The efficient MCU instructions allow users to program the powerful custom applications. The system frequency of HT86XXX can be up to 8MHz under 2.4V and include a HALT function to reduce power consumption.
Selection Table
Body Voice ROM size Voice length Note: HT86072 1536K-bit 72 sec HT86144 3072K-bit 144 sec HT86192 4096K-bit 192 sec HT86384 8192K-bit 384 sec HT86576 12288K-bit 576 sec HT86768 16392K-bit 768 sec
* Voice length is estimated by 21K-bit data rate
Rev. 1.70
1
May 6, 2004
HT86XXX
Block Diagram
S Y S C L K /4 STACK0 STACK1 STACK2 P ro g ra m C o u n te r P ro g ra m ROM STACK3 STACK4 STACK5 STACK6 STACK7 In te rru p t C ir c u it IN T M U X
TM R0 TM R0C
P C 4 /T M R 0
1 6 b it
S Y S C L K /4 M U X
IN T C
TM R1 TM R1C 1 6 b it
P C 5 /T M R 1
In s tr u c tio n R e g is te r
MP0 MP1 M
U X
DATA M e m o ry
W DTS M 256 W D T P r e s c a le r
U X
W DTRC OSC S Y S C L K /4
PCC In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n S h ifte r PAC PA OSC2 OS RE VD VS S C1 S D ACC H ALT E N /D IS MUX PC PBC STATUS PB
PORT C
PC0~PC6
PORT B
PB0~PB7
PORT A
PA0~PA7
TM R2
S Y S C L K /4
L V D /L V R
TM R2C 1 6 - b it
S Y S C L K /4 3 2 7 6 8 H z C ry s ta l (X IN a n d X O U T ) 8 -s ta g e P r e s c a le r M U X
TM R3
TM R3C
8 - b it
3 - b it V o lu m e C o n tro l
1 2 - b it D /A
Rev. 1.70
2
May 6, 2004
HT86XXX
Pin Assignment
100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC NC NC NC NC NC NC NC PA5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PA4 NC NC NC NC 4 5 6 7 8 9 10 11 12 13 14 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC VSS 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC NC NC OSC2 OSC1 IN T RES AUD TEST VDDA VDD VSSA PA3 PA2 PA1 PA0 NC VSS VDD AUD IN T NC NC NC RES OSC1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PA7 PA6 NC NC NC NC NC NC NC NC NC NC P NC NC NC OSC2 P P P P P P P P P NC NC NC NC NC NC A7 A6 A5 A4 A3 A2 A1 A0 B7 NC NC NC NC B6 NC
9 8 7 6 5 4 3 2 1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC OSC2 NC NC OSC1 NC IN T NC NC NC RES
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50
H T860 H T861 H T865 10
72 92 76 0
/H T /H T /H T QF
86144 86384 86768 P -A
H T 8 6 0 7 2 /H T 8 6 1 4 4 H T 8 6 1 9 2 /H T 8 6 3 8 4 2 8 S O P -A
H T 8 6 5 7 6 /H T 8 6 7 6 8 3 2 S O P -B
AUD TES VDD VDD VSS VSS PC0 PC1 PC2 PC3 PC4 PC5 PC6 XOU PB0 PB1 PB2 PB3 PB4 PB5 /X IN T T A A
Pad Assignment
HT86072
PA7
1
PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
(0 ,0 ) 34 OSC2
33 32
20 21 22 23 24 25 26 27 28 29 30 31
OSC1 IN T
* The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.70 3 May 6, 2004
RE AU TE VD VD VS VS PC PC PC PC PC PC PC XO PB PB S D ST DA D SA 1 0 S 0 1 2 3 4 5 6 /X IN UT
Chip size: 22152830 (mm)2
HT86XXX
HT86144
(0 ,0 )
PA PA PA PA PA PA PA PA PB 7 PB PB PB PB PB 2 6 5 4 3
7
1
6
2 3 4 5 6 7 8 9
5 4 3 2 1 0
34
OSC2
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
33 32 31
OSC1 IN T
RES
* The IC substrate should be connected to VSS in the PCB layout artwork.
TE VD VD VS VS PC PC PC PC PC PC PC XO PB PB ST DA D SA 1 0 S 0 1 2 3 4 5 6 /X IN UT
AUD
Chip size: 22153635 (mm)2
Rev. 1.70
4
May 6, 2004
HT86XXX
HT86192
(0 ,0 )
PA PA PA PA PA PA PA PA PB 7 PB6 PB5 PB4 PB3 PB2
7
1
6
2 3 4 5 6 7 8 9
5 4 3 2 1 0
34
OSC2
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
33 32 26 27 28 29 30 31
OSC1 IN T
* The IC substrate should be connected to VSS in the PCB layout artwork.
PB1
PC5 P C 6 /X IN XOUT PB0
RES
Chip size: 22154175 (mm)2
PC4
PC1 PC2 PC3
AU TE VD VD VS VS PC D ST DA D SA S 0
Rev. 1.70
5
May 6, 2004
HT86XXX
HT86384
(0 ,0 )
PA7
1 2 3 4 5 6 7 8
PA6 PA5 PA PA PA PA 1 0 7 6 5 PA PB PB PB PB4 PB3 PB2 4 3 2
34
OSC2
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
33 32 31
OSC1 IN T
RES
* The IC substrate should be connected to VSS in the PCB layout artwork.
PB1
PC5 P C 6 /X IN XOUT PB0
Chip size: 22156325 (mm)2
PC3 PC4
PC0 PC1 PC2
VD VD VS VS S DA D SA
AUD TEST
Rev. 1.70
6
May 6, 2004
HT86XXX
HT86576
(0 ,0 )
PA7 1 2 3 4 5 6 7 8 9 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7
34
OSC2
33 28 29 30 25 26 27 VSSA VDD VDDA VSS TEST AUD 31 32
OSC1
10 11 12 13 14 15 16 17 18 19 P C 6 /X IN PC5 XOUT PB6 PB5 PB4 PB3 PB2 PB1 PB0
20 PC4
21 22 PC3 PC2
23 PC1
24 PC0
RES
IN T
Chip size: 40604740 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.70
7
May 6, 2004
HT86XXX
HT86768
(0 ,0 )
PA7 1 2 3 4 5 6 7 8 9 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7
34
OSC2
33 27 28 29 30 31 32
OSC1
10 11 12 13 14 15 16 17 18 19 20 PC PC PC XO PB PB PB PB PB PB PB 6 5 4 3 2 1 0 4 5 6 /X IN UT
21 22 23 24 25 26 PC3 PC2
RE AU TE VD VD VS VS PC PC S D ST DA D SA S 1 0
IN T
Chip size: 40605805 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.70 8 May 6, 2004
HT86XXX
Pad Coordinates
HT86072 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 HT86144 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -746.600 -636.000 -536.000 Y -284.211 -394.811 -494.811 -605.411 -705.411 -816.011 -916.011 -1026.611 -1126.611 -1237.211 -1337.211 -1447.811 -1547.811 -1658.411 -1651.761 -1651.761 -1651.761 Pad No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X -425.400 -325.400 -214.800 -114.800 -4.200 95.800 206.400 316.215 416.415 516.415 616.415 721.415 833.215 946.426 940.115 940.065 940.065 Y -1651.761 -1651.761 -1651.761 -1651.761 -1651.761 -1651.761 -1651.761 -1651.811 -1651.811 -1614.761 -1614.761 -1614.761 -1614.761 -1614.761 -1409.750 -1294.287 -616.435 X -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -746.600 -636.000 -536.000 Y 118.250 7.650 -92.350 -202.950 -302.950 -413.550 -513.550 -624.150 -724.150 -834.750 -934.750 -1045.350 -1145.350 -1255.950 -1249.300 -1249.300 -1249.300 Pad No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X -425.400 -325.400 -214.800 -114.800 -4.200 95.800 206.400 316.215 416.415 516.415 616.415 721.415 833.215 946.426 940.115 940.065 940.065 Y -1249.300 -1249.300 -1249.300 -1249.300 -1249.300 -1249.300 -1249.300 -1249.350 -1249.350 -1212.300 -1212.300 -1212.300 -1212.300 -1212.300 -1007.289 -891.826 -213.974
Rev. 1.70
9
May 6, 2004
HT86XXX
HT86192 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 HT86384 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 HT86576 Pad No. 1 2 3 4 5 6 7 8 X -1864.850 -1864.850 -1864.850 -1864.850 -1864.850 -1864.850 -1864.850 -1864.850 Y -1331.600 -1442.200 -1542.200 -1652.800 -1752.800 -1863.400 -1963.400 -2074.000 Pad No. 18 19 20 21 22 23 24 25 X -764.350 -663.350 -552.750 659.200 769.800 869.800 980.400 1110.300 Y -2204.850 -2204.850 -2204.850 -2204.850 -2204.850 -2204.850 -2204.850 -2204.900 X -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -746.600 -636.000 -536.000 Y -1627.476 -1738.076 -1838.076 -1948.676 -2048.676 -2159.276 -2259.276 -2369.876 -2469.876 -2580.476 -2680.476 -2791.076 -2891.076 -3001.676 -2995.026 -2995.026 -2995.026 Pad No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X -425.400 -325.400 -214.800 -114.800 -4.200 95.800 206.400 316.215 416.415 516.415 616.415 721.415 833.215 946.426 940.115 940.065 940.065 Y -2995.026 -2995.026 -2995.026 -2995.026 -2995.026 -2995.026 -2995.026 -2995.076 -2995.076 -2958.026 -2958.026 -2958.026 -2958.026 -2958.026 -2753.015 -2637.552 -1959.700 X -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -942.295 -746.600 -636.000 -536.000 Y -553.325 -663.925 -763.925 -874.525 -974.525 -1085.125 -1185.125 -1295.725 -1395.725 -1506.325 -1606.325 -1716.925 -1816.925 -1927.525 -1920.875 -1920.875 -1920.875 Pad No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X -425.400 -325.400 -214.800 -114.800 -4.200 95.800 206.400 316.215 416.415 516.415 616.415 721.415 833.215 946.426 940.115 940.065 940.065 Y -1920.875 -1920.875 -1920.875 -1920.875 -1920.875 -1920.875 -1920.875 -1920.925 -1920.925 -1883.875 -1883.875 -1883.875 -1883.875 -1883.875 -1678.864 -1563.401 -885.549
Rev. 1.70
10
May 6, 2004
HT86XXX
Pad No. 9 10 11 12 13 14 15 16 17 HT86768 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X -1864.850 -1864.850 -1864.850 -1864.850 -1864.850 -1864.850 -1864.850 -1864.850 -1864.850 -1618.550 -1518.550 -1407.950 -1307.950 -1197.350 -1097.350 -986.750 -881.025 Y -1864.100 -1974.700 -2074.700 -2185.300 -2285.300 -2395.900 -2495.900 -2606.500 -2706.500 -2737.350 -2737.350 -2737.350 -2737.350 -2737.350 -2737.350 -2737.350 -2737.350 Pad No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X -764.350 -663.350 -552.750 659.200 769.800 869.800 980.400 1110.300 1210.500 1310.510 1425.500 1530.500 1642.300 1755.511 1860.559 1859.150 1859.150 Y -2737.350 -2737.350 -2737.350 -2737.350 -2737.350 -2737.350 -2737.350 -2737.400 -2737.400 -2700.350 -2700.350 -2700.350 -2700.350 -2700.350 -2700.350 -2468.026 -1790.174 X -1864.850 -1618.550 -1518.550 -1407.950 -1307.950 -1197.350 -1097.350 -986.750 -881.025 Y -2174.000 -2204.850 -2204.850 -2204.850 -2204.850 -2204.850 -2204.850 -2204.850 -2204.850 Pad No. 26 27 28 29 30 31 32 33 34 X 1210.500 1310.510 1425.500 1530.500 1642.300 1755.511 1860.559 1859.150 1859.150 Y -2204.900 -2167.850 -2167.850 -2167.850 -2167.850 -2167.850 -2167.850 -1935.526 -1257.674
Pad Description
Pad Name PA0~PA7 I/O I/O Mask Option Wake-up, Pull-high or None Pull-high or None Pull-high or None 32kHz RTC 3/4 3/4 3/4 3/4 3/4 Description Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input by mask option. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (mask option). Bidirectional 8-bit I/O port. Software instructions determine the CMOS output or Schmitt trigger input (pull-high resistor depending on mask option). Bidirectional 7-bit I/O port. Software instructions determine the CMOS output or Schmitt trigger input (pull-high resistor depending on mask option). XIN is pin-shared with PC6 Connected an external 32kHz crystal to XIN and XOUT. Negative power supply, ground Positive power supply DAC power supply DAC negative power supply, ground Schmitt trigger reset input, active low
PB0~PB7
I/O
PC0~PC5 PC6/XIN XOUT VSS VDD VDDA VSSA RES
I/O 3/4 3/4 3/4 3/4 3/4 I
Rev. 1.70
11
May 6, 2004
HT86XXX
Pad Name I/O Mask Option Description
INT
I
External interrupt Schmitt trigger input without pull-high resistor. Choice Falling Edge Trigger falling edge trigger or falling/rising edge trigger by mask option. Falling or Falling/Rising Edge edge triggered active on a high to low transition. Rising edge triggered Trigger active on a low to high transition. OSC1 and OSC2 are connected to an RC network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. The system clock may come from the crystal, the two pins cannot be floating. Audio output for driving a external transistor or for driving HT82V733 No connection No connection (open)
OSC1 OSC2
3/4
RC or Crystal
AUD NC TEST
O 3/4 3/4
3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+5.5V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-20C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD ISTB1 ISTB2 IDD IOL IOH IO VIL1 VIH1 VIL2 VIH2 Parameter Operating Voltage Standby Current (Watchdog Off) Test Conditions VDD 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 3V 3V 3V Conditions 3/4 fSYS=4MHz/8MHz No load, system HALT
Ta=25C Min. Typ. Max. Unit 2.4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 ROSC=100kW For HT86072, HT86144, ROSC=62kW HT86192, HT86384 only ROSC=240kW For HT86576, HT86768 ROSC=150kW only 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 4 10 -2 -5 -3 -6 1.3 1.8 1.5 2.4 4.0 8.0 4.0 8.0 5.2 1 2 7 10 3 7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 MHz V mA mA mA
Standby Current(Watchdog On)
No load, system HALT No load, fSYS=4MHz VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD
Operating Current (Crystal OSC)
I/O Port Sink Current
mA
I/O Port Source Current
mA
AUD Source Current Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Reset Low Voltage (RES) Reset High Voltage (RES)
mA V V V V
fSYS
System Frequency
3V
Rev. 1.70
12
May 6, 2004
HT86XXX
Symbol RPH Parameter Pull-high Resistance Test Conditions VDD 3V 5V Conditions 3/4 Min. Typ. Max. Unit 20 10 60 30 100 50 kW
A.C. Characteristics
Symbol fSYS1 fSYS2 fTIMER Parameter System Clock (RC OSC) System Clock (Crystal OSC) Timer Input Frequency Test Conditions VDD 3/4 2.4V~5.2V 3/4 2.4V~5.2V 3/4 2.4V~5.2V 3V 5V 3/4 3/4 Conditions
Ta=25C Min. Typ. Max. Unit 4 4 0 45 32 11 8 3/4 3/4 1 3/4 1 3/4 3/4 3/4 90 65 23 17 1024 7.812 3/4 1024 3/4 8 8 8 180 130 46 33 3/4 3/4 3/4 3/4 3/4 MHz MHz MHz ms ms ms ms tSYS ms ms tSYS ms
tWDTOSC Watchdog Oscillator Period tWDT1 tWDT2 tWDT3 tRES tSST tINT
Watchdog Time-out Period 3V Without WDT prescaler (WDT OSC) 5V Watchdog Time-out Period (Sys3/4 Without WDT prescaler tem Clock) Watchdog Time-out Period (RTC 3/4 Without WDT prescaler OSC) External Reset Low Pulse Width 3/4 System Start-up Timer Period Interrupt Pulse Width 3/4 3/4 3/4 3/4 Wake-up from HALT
Characteristics Curves
HT86072/HT86144/HT86192/HT86384 R vs. F Characteristics Curve
H T 8 6 0 7 2 /H T 8 6 1 4 4 /H T 8 6 1 9 2 /H T 8 6 3 8 4 R v s . F C h a r t
10
8 F re q u e n c y (M H z ) 6
4 .5 V
4
3 .0 V
2 55 65 75 85 95 105 115
R
(k W )
Rev. 1.70
13
May 6, 2004
HT86XXX
HT86072/HT86144/HT86192/HT86384 V vs. F Characteristics Curve
H T 8 6 0 7 2 /H T 8 6 1 4 4 /H T 8 6 1 9 2 /H T 8 6 3 8 4 V v s . F C h a r t (F o r 3 .0 V )
10
8 M H z /6 2 k W
8 F re q u e n c y (M H z ) 6 M H z /7 7 k W 6 4 M H z /1 0 5 k W 4
2 2 .4 2 .7 3 3 .3 3 .6 3 .9 4 .2 4 .5 4 .8 5 .2
V
DD
(V )
H T 8 6 0 7 2 /H T 8 6 1 4 4 /H T 8 6 1 9 2 /H T 8 6 3 8 4 V v s . F C h a r t (F o r 4 .5 V )
10 8 M H z /6 9 k W 8 F re q u e n c y (M H z ) 6 M H z /8 4 k W 6 4 M H z /1 1 5 k W 4
2 2 .4 2 .7 3 3 .3 3 .6 3 .9 4 .2 4 .5 4 .8 5 .2
V
DD
(V )
Rev. 1.70
14
May 6, 2004
HT86XXX
HT86576/HT86768 R vs. F Characteristics Curve
H T 8 6 5 7 6 /H T 8 6 7 6 8 R v s . F C h a r t
10 F re q u e n c y (M H z ) 8 6 4 2 150 180 200 220 240 270 3 .0 V 4 .5 V 300
R
(k W )
HT86576/HT86768 V vs. F Characteristics Curve
H T 8 6 5 7 6 /H T 8 6 7 6 8 V v s . F C h a r t (F o r 3 .0 V )
10 8 6 4 2 2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 3 .8 4 4 .2 4 .4 4 .5 4 .6 4 .8 5 5 .2 8 M H z /1 5 5 k W 6 M H z /1 9 3 k W 4 M H z /2 7 9 k W
F re q u e n c y (M H z )
V
DD
(V )
Rev. 1.70
15
May 6, 2004
HT86XXX
H T 8 6 5 7 6 /H T 8 6 7 6 8 V v s . F C h a r t (F o r 4 .5 V )
10 F re q u e n c y (M H z ) 8 6 4 2 2 .4 2 .6 2 .8 3 3 .2 3 .4 3 .6 3 .8 4 4 .2 4 .4 4 .5 4 .6 4 .8 5 5 .2 8 M H z /1 4 7 k W 6 M H z /1 9 2 k W 4 M H z /2 7 5 k W
V
DD
(V )
Rev. 1.70
16
May 6, 2004
HT86XXX
Functional Description
Execution Flow The system clock for the HT86XXX series is derived from either a crystal or an RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction.
T1 T2 T3 T4 T1 T2
Program Counter - PC The 13-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
T3 T4 T1 T2 T3 T4
S y s te m
C lo c k
O S C ( R C o n ly ) P1 P2 P3 P4 PC PC PC+1 PC+2 In te rn a l P hase C lo c k s
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *12 0 0 0 0 0 0 *12 #12 S12 *11 0 0 0 0 0 0 *11 #11 S11 *10 0 0 0 0 0 0 *10 #10 S10 *9 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 PC+2 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *5 0 0 0 0 0 0 *4 0 0 0 0 1 1 *3 0 0 1 1 0 0 *2 0 1 0 1 0 1 *1 0 0 0 0 0 0 *0 0 0 0 0 0 0
Mode Initial Reset External or Serial Input Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Timer Counter 2 Overflow Timer Counter 3 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter Note: *12~*0: Program counter bits #12~#0: Instruction code bits S12~S0: Stack register bits @7~@0: PCL bits
Rev. 1.70
17
May 6, 2004
HT86XXX
subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the program counter (PCL) is a read/write register (06H). Moving data into the PCL performs a short jump. The destination must be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program Memory - ROM The program memory stores the program instructions that are to be executed. It also includes data, table and interrupt entries, addressed by the program counter along with the table pointer. The program memory size for HT86XXX is 819216 bits. Certain locations in the program memory are reserved for special usage:
* Location 000H * Location 008H
This area is reserved for the 16-bit Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 008H and begins execution.
* Location 00CH
This area is reserved for the 16-bit Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 00CH and begins execution.
* Location 010H
This area is reserved for the 16-bit Timer Counter 2 interrupt service program. If a timer interrupt results from a Timer Counter 2 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 010H and begins execution.
* Location 014H
This area is reserved for program initialization. The program always begins execution at location 000H each time the system is reset.
* Location 004H
This area is reserved for the 8-bit Timer Counter 3 interrupt service program. If a timer interrupt results from a Timer Counter 3 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 014H and begins execution. Table location Any location in the ROM space can be used as look up tables. The instructions TABRDC [m] (used for any bank) and TABRDL [m] (only used for last page of program ROM) transfer the contents of the lower-order byte to the specified data memory [m], and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined. The higher-order bytes of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBHP, TBLP) is a read/write register, which indicates the table location. Because TBHP is unknown after power on reset, TBHP must be set specified.
This area is reserved for the external interrupt service program. If the INT input pin is activated, and the interrupt is enabled and the stack is not full, the program will jump to location 004H and begins execution.
0000H 0004H 0008H 000CH 0010H 0014H 0015H In itia l A d d r e s s E x te r n a l In te r r u p t S u b r o u tin e T im e r 0 In te r r u p t S u b r o u tin e T im e r 1 In te r r u p t S u b r o u tin e T im e r 2 In te r r u p t S u b r o u tin e T im e r 3 In te r r u p t S u b r o u tin e ( R T C ) P ro g ra m ROM
1FFFH
Program Memory Table Location *12 P12 1 *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Instruction TABRDC [m] TABRDL [m]
Table Location Note: *12~*0: Current program ROM table P12~P8: Write P12~P8 to TBHP pointer register @7~@0: Write @7~@0 to TBLP pointer register
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Stack Register - Stack The stack register is a special part of the memory used to save the contents of the program counter (PC). This stack is organized into eight levels. It is neither part of the data nor part of the program space, and cannot be read or written to. Its activated level is indexed by a stack pointer (SP) and cannot be read or written to. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. The program counter is restored to its previous value from the stack at the end of subroutine or interrupt routine, which is signaled by return instruction (RET or RETI). After a chip resets, SP will point to the top of the stack. The interrupt request flag will be recorded but the acknowledgment will be inhibited when the stack is full and a non-masked interrupt takes place. After the stack pointer is decremented (by RET or RETI), the interrupt request will be serviced. This feature prevents stack overflow and allows programmers to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry is lost. Data Memory - RAM The data memory is designed with 2088 bits. The data memory is further divided into two functional groups, namely, special function registers (00H~2AH) and general purpose user data memory (30H~FFH). Although most of them can be read or be written to, some are read only. The special function registers include an indirect addressing register (R0:00H), memory pointer register Address RAM Mapping 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH R0 MP0 R1 MP1 Unused ACC PCL TBLP TBLH WDTS STATUS INTC TMR0H TMR0L TMR0C R/W R/W R/W R R/W R/W R/W R/W R/W R/W Accumulator Program counter lower-order byte address Table pointer lower-order byte address Table higher-order byte content register Watchdog Timer option setting register Status register Interrupt control register 0 Timer/Event counter 0 higher-byte register Timer/Event counter 0 lower-byte register Timer/Event counter 0 control register Read/Write R/W R/W R/W R/W (MP0:01H), accumulator (ACC:05H), program counter lower-order byte register (PCL:06H), table pointer (TBLP:07H), table higher-order byte register (TBLH:08H), status register (STATUS:0AH), interrupt control register 0 (INTC:0BH), Timer/Event Counter 0 (TMR0H:0CH,TMR0L:0DH), Timer/Event Counter 0 control register (TMR0C:0EH), Timer/Event Counter 1 (TMR1H:0FH, TMR1L:10H), Timer/Event Counter 1 co n t r o l r e g i st e r ( T M R 1 C : 1 1 H ) , I / O r e g i st e r s (PA:12H,PB:14H,PC:16H), I/O control registers (PAC:13H,PBC:15H,PCC:17H), voice ROM address l a t ch 0 [ 2 3 : 0 ] ( L A T C H 0 H : 1 8 H , L A T C H 0 M : 1 9 H , LATCH0L:1AH), voice ROM address latch1[23:0] (LATCH1H:1BH, LATCH1M:1CH, LATCH1L:1DH), interrupt control register 1 (INTCH:1EH), table pointer higher-order byte register (TBHP:1FH), Timer Counter 2 (TMR2H:20H, TMR2L:21H), Timer Counter 2 control register (TMR2C:22H), Timer Counter 3 (TMR3L:24H), Timer Counter 3 control register (TMR3C:25H), voice co n t r o l r e g i st e r ( V O I C E C : 2 6 H ) , D A C o u t p u t (DAH:27H,DAL:28H), volume control register ( V O L : 2 9 H ) , vo i ce R O M l a t ch d a t a r e g i st e r (LATCHD:2AH). The general purpose data memory, addressed from 30H~FFH, is used for data and control information under instruction commands. The areas in the RAM can directly handle the arithmetic, logic, increment, decrement, and rotate operations. Except some dedicated bits, each bit in the RAM can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the memory pointer register 0 (MP0:01H) or the Memory Pointer register 1 (MP1:03H).
Description Indirect addressing register 0 Memory pointer 0 Indirect addressing register 1 Memory pointer 1
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Address RAM Mapping 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC LATCH0H LATCH0M LATCH0L LATCH1H LATCH1M LATCH1L INTCH TBHP TMR2H TMR2L TMR2C Unused TMR3L TMR3C VOICEC DAL DAH VOL LATCHD R/W R/W R/W Timer Counter 3 lower-byte register Timer Counter 3 control register Voice control register Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Timer/Event counter 1 higher-byte register Timer/Event counter 1 lower-byte register Timer/Event counter 1 control register Port A I/O data register Port A I/O control register Port B I/O data register Port B I/O control register Port C I/O data register Port C I/O control register Voice ROM address latch 0 [A23~A16] Voice ROM address latch 0 [A15~A8] Voice ROM address latch 0 [A7~A0] Voice ROM address latch 1 [A23~A16] Voice ROM address latch 1 [A15~A8] Voice ROM address latch 1 [A7~A0] Interrupt control register 1 Table pointer higher-order byte register Timer Counter 2 higher-byte register Timer Counter 2 lower-byte register Timer Counter 2 control register
R/W, higher-nibble DAC output data D3~D0 to DAL7~DAL4 available only R/W DAC output data D11~D4 to DAH7~DAH0
R/W, higher-nibble Volume control register, and volume controlled by VOL7~VOL5 available only R Voice ROM data register
2BH~2FH Unused 30H~FFH User data RAM R/W User data RAM
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Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining the corresponding indirect addressing registers. Accumulator - ACC (05H) The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc)
Except the TO and PD flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PD flags. Operations related to the status register, however, may yield different results from those intended. The TO and PD flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Interrupts The HT86XXX provides an external interrupt, three 16-bit programmable timer interrupts, and an 8-bit programmable timer interrupt. The Interrupt Control registers (INTC:0BH, INTCH:1EH) contain the interrupt control bits to set to enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI bit and the corresponding INTC/INTCH bit may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. Function
Status Register - STATUS (0AH) This 8-bit STATUS register (0AH) consists of a zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Labels C Bits 0
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared by system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status Register
AC Z OV PD TO 3/4
1 2 3 4 5 6, 7
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As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at the specified location(s) in the program memory. Only the program counter is pushed onto the stack. The programmer must save the contents of the register or status register (STATUS) in advance if they are altered by an interrupt service program which corrupts the desired control sequence. External interrupt is triggered by a high-to-low/ low-to-high transition of INT pin which sets the related interrupt request flag (EIF:bit 4 of INTC). When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event counter 0 interrupt request flag (T0F:bit 5 of INTC), caused by a Timer/Event Counter 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (T1F:bit 6 of INTC), caused by a Timer/Event Counter 1 overflow. When the interrupt is enabled, and the stack is not full and the T1F bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. The internal Timer Counter 2 interrupt is initialized by setting the Timer Counter 2 interrupt request flag (T2F:bit 0 of INTCH), caused by a Timer Counter 2 overflow. When the interrupt is enabled, and the stack is not full and the T2F bit is set, a subroutine call to location 10H will occur. The related interrupt request flag (T2F) will be reset and the EMI bit cleared to disable further interrupts. The internal Timer Counter 3 interrupt is initialized by setting the Timer Counter 3 interrupt request flag (T3F:bit 1 of INTCH), caused by a Timer Counter 3 overflow. When the interrupt is enabled, and the stack is not full and the T3F bit is set, a subroutine call to location 14H will occur. The related interrupt request flag (T3F) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledges are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To INTC (0BH) return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. The Timer/Event Counter 0/1 interrupt request flag (T0F/T1F) which enables Timer/Event Counter 0/1 control bit (ET0I/ET1I), the Timer Counter 2/3 interrupt request flag (T2F/T3F) which enables Timer Counter 2/3 control bit (ET2I/ET3I), and external interrupt request flag (EIF) which enables external interrupt control bit (EEI) form the interrupt control register (INTC:0BH and INTCH:1EH). EMI, EEI, ET0I, ET1I, ET2I, and ET3I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt begin serviced. Once the interrupt request flags (T0F, T1F, T2F, T3F, EIF) are set, they will remain in the INTC/INTCH register until the interrupts are serviced or cleared by a software instruction. It is recommended that application programs do not use CALL subroutines within an interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt enable is not well controlled, once a CALL subroutine if used in the interrupt subroutine will corrupt the original control sequence. Register Bit No. Label 0 Function
Controls the master (global) EMI interrupt (1= enabled; 0= disabled) EEI ET0I ET1I EIF T0F T1F 3/4 Controls the external interrupt (1= enabled; 0= disabled) Controls the timer 0 interrupt (1= enabled; 0= disabled) Controls the timer 1 interrupt (1= enabled; 0= disabled) External interrupt request flag (1= active; 0= inactive) Timer 0 request flag (1= active; 0= inactive) Timer 1 request flag (1= active; 0= inactive) Unused bit, read as 0
1 2 3 4 5 6 7
INTC0 Register
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Register Bit No. Label 0 1 INTCH (1EH) 2, 3 4 5 6, 7 Function with VDD, temperature, and the chip itself due to process variations. It is therefore not suitable for timing sensitive operations where accurate oscillator frequency is desired. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. There is another oscillator circuit designed for Timer3s clock source as the RTC time base which is determined by mask option. If the mask option determines that Timer3s clock source is from a 32kHz crystal, then a 32kHz crystal should be connected to XIN and XOUT. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with period 78ms normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20 ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out period can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of WDTS(09H)) can give different time-out period. If WS2, WS1, WS0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
Controls the timer 2 interrupt ET2I (1= enabled; 0= disabled) ET3I 3/4 Controls the timer 3 interrupt (1= enabled; 0= disabled) Unused bit, read as 0
Timer 2 interrupt request flag T2F (1= active; 0= inactive) T3F 3/4 Timer 3 interrupt request flag (1= active; 0= inactive) Unused bit, read as 0
INTC1 Register Interrupt Source External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Timer Counter 2 Overflow Timer Counter 3 Overflow Oscillator Configuration The HT86XXX provides two types of oscillator circuit for the system clock, i.e., RC oscillator and crystal oscillator. No matter what type of oscillator, the signal is used for the system clock. The HALT mode stops the system oscillator and ignores external signal to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 30kW to 680kW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary Priority 1 2 3 4 5 Vector 04H 08H 0CH 10H 14H
OSC1 V
DD
OSC1
X IN (P C 6 )
OSC2 C r y s ta l O s c illa to r
fS
YS
/4
RC
OSC2
O s c illa to r
XOUT R T C O s c illa to r
System Oscillator
S y s te m C lo c k /4 M ask O p tio n S e le c t W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
W DT OSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm re set only the PC and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler), three methods are adopted; external reset (external reset (a low level to RES), software instructions, or a HALT instruction. The software instruction is CLR WDT and execution of the CLR WDT instruction will clear the WDT. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 WDTS Register Power Down - HALT The HALT mode is initialized by a HALT instruction and results in the following: The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected).
* The contents of the on chip RAM and registers remain
instruction. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled by the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. Once a wake-up event occurs, it takes 1024 system clock period to resume normal operation. In other words, a dummy cycle period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next instruction execution, this will be executed immediately after a dummy period is finished. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Reset There are 3 ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
unchanged.
* WDT and WDT prescaler will be cleared and recount
again.
* All I/O ports maintain their their original status. * The PD flag is set and the TO flag is cleared.
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during any other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PD flag and TO flag, the program can distinguish between different chip resets. TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. By examining the TO and PD flags, the reason for the chip reset can be determined. The PD flag is cleared when the system powers-up or executes the CLR WDT instruction, and is set when the HALT instruction is executed. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the PC and SP. The other maintain their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by a mask option. Awakening from an I/O port stimulus, the program will resume execution of the next
Note: u stands for unchanged To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses after a system power up or when awakening from a HALT state. When a system power up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay.
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VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Timing Chart
V
DD
There are three registers related to Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH). Writing to TMR0L only writes the data into a low byte buffer. Writing to TMR0H will write the data and the contents of the low byte buffer into the Timer/Event Counter 0 preload register (16-bit) simultaneously. The Timer/Event Counter 0 preload register is changed only by a write to TMR0H operation. Writing to TMR0L will keep the Timer/Event Counter 0 preload register unchanged. Reading TMR0H will also latch the TMR0L into the low byte buffer to avoid false timing problems. Reading the TMR0L only returns the value from the low byte buffer which may be a previously loaded value. In other words, the low byte of Timer/Event Counter 0 cannot be read directly. It must read the TMR0H first to ensure that the low byte contents of Timer/Event Counter 0 are latched into the buffer. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). The Timer/Event Counter 1 operates in the same manner as Timer/Event Counter 0. Label 3/4 TE Bits Function 0~2 Unused bit, read as 0 3 To define the TMR0/TMR1 active edge of timer/event counter (0=active on low to high; 1=active on high to low) To enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode (TMR1, TMR0) 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C/TMR1C Register Label 3/4 TE Bits Function
RES
Reset Circuit
HALT W DT W DT T im e - o u t R eset
W a rm
R eset
RES SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tin g C o ld R eset
OSCI
TON 3/4
4 5
Reset Configuration The function unit chip reset status are shown below. PC Interrupt Prescaler WDT Timer/event counter Input/output ports SP 000H Disable Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
TM0, TM1
6 7
0~2 Unused bit, read as 0 3 To define the TMR0/TMR1 active edge of timer/event counter (0=active on low to high; 1=active on high to low) To enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode (TMR1, TMR0) 01=Unused 10=Timer mode (internal clock) 11=Unused 00=Unused TMR2C Register
Timer/Event Counter 0/1 There are four timer counters are implemented in the HT86XXX. The Timer/Event Counter 0 and 1 contain 16-bit programmable count-up counters whose clock may come from an external source or the system clock divided by 4 (T1). Using the internal instruction clock (T1), there is only one reference time base. The external clock input allows the user to count external events, measure time intervals or pulse width, or to generate an accurate time base.
TON 3/4
4 5
TM0, TM1
6 7
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S y s te m TM R0 TM R1 C lo c k /4 D a ta B u s TM 1 TM 0 T im e r /E v e n t C o u n te r 0 /1 P r e lo a d R e g is te r R e lo a d
TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r 0 /1 O v e r flo w to In te rru p t
L o w B y te B u ffe r
Timer/Event Counter 0/1 The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options. The Timer/Event Counter 1 has the same options as the Timer/Event Counter 0 and is defined by TMR1C. The timer/event counter control registers define the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which implies that the clock source comes from an external (TMR0/TMR1 is connected to PC4/PC5) pin. The timer mode functions as a normal timer with the clock source coming from the instruction clock. The pulse width measurement mode can be used to count the high o r lo w l ev e l d u r at i o n of a n ex t e r n a l si g n a l (TMR0/TMR1). The counting method is based on the instruction clock. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates a corresponding interrupt request flag (T0F/T1F; bit 5/6 of INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR0/TMR1 has received a transient from low to high (or high to low; if the TE bit is 0) it will start counting until the TMR0/TMR1 returns to the original level and resets TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. When TON is set again, the cycle measurement will function again as long as it receives further transient pulses. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like in the other two modes. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the pulse width measurement mode, TON will be cleared automatically after the measurement cycle is complete. But in the other two modes TON can only be reset by instruction. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service. In the case of a Timer/Event Counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter will only be kept in the timer/event counter preload register. The timer/event counter will continue to operate until an overflow occurs. When the timer/event counter (reading TMR0H/ TMR1H) is read, the clock will be blocked to avoid errors. As this may result in a counting error, this must be taken into consideration by the programmer. Timer Counter 2 The timer counter TMR2 is also a 16-bit programmable count-up counter. It operates in the same manner as Timer/Event Counter 0/1, but the clock source of TMR2 is from only internal instruction cycle (T1). Therefore only (TM1,TM0)=(1,0) is allowable.
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S y s te m C lo c k /4 GND TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r 2 O v e r flo w to In te rru p t D a ta B u s TM 1 TM 0 T im e r /E v e n t C o u n te r 2 P r e lo a d R e g is te r R e lo a d
L o w B y te B u ffe r
Timer Counter 2
Timer Counter 3 (RTC Time Base) The timer counter TMR3 is an 8-bit programmable count-up counter. Its counting is as the same manner as Timer Event Counter 0/1 and Timer Counter 2, but the clock source of TMR3 can be from internal instruction cycle (T1) or external 32kHz crystal which is connected to XIN and XOUT. The TMR3s clock source is determined by mask option. If the 32kHz crystal is enabled, then TMR3s clock source is 32kHz which is from XIN and XOUT. If the 32kHz crystal is disabled, then TMR3s clock source is internal T1. The TMR3 is internal clock source only, i.e. (TM1,TM0)=(1,0). There is a 3-bit prescaler (TMR3S2,TMR3S1,TMR3S0) which defines different division ratio of TMR3s clock source.
Label
Bits
Function
To define the operating clock source (TMR3S2, TMR3S1, TMR3S0) 000: clock source/2 001: clock source/4 TMR3S2, 010: clock source/8 TMR3S1, 0~2 011: clock source/16 TMR3S0 100: clock source/32 101: clock source/64 110: clock source/128 111: clock source/256 To define the TMR3 active edge of timer/event counter (0=active on low to high; 1=active on high to low) To enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode (TM1, TM0) 01=Unused 10=Timer mode (internal clock) 11=Unused 00=Unused TMR3 Register
TE
3
TON 3/4
4 5
TM0, TM1
6 7
(T M R 3 S 2 , T M R 3 S 1 , T M R 3 S 0 ) S y s te m C lo c k /4 M ask O p tio n 8 -S ta g e P r e s c a le r TON T im e r C o u n te r 3 P r e lo a d R e g is te r
D a ta B u s R e lo a d
3 2 K C ry s ta l
T im e r C o u n te r 3
O v e r flo w to In te rru p t
Timer Counter 3
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The registers states are summarized in the following table. Register Reset (Power On) PC MP0 MP1 ACC TBLP TBLH WDTS STATUS INTC TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC TMR2H TMR2L TMR2C TMR3L TMR3C INTCH TBHP DAL DAH VOL VOICEC LATCH0H LATCH0M LATCH0L LATCH1H LATCH1M LATCH1L LATCHD Note: 0000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx 00-0 1xxx -000 ---0 ---x xxxx xxxx ---xxxx xxxx xxx- ---0--0 -00xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx WDT Time-out RES Reset (Normal Operation) (Normal Operation) 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 --1u uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu 00-0 1uuu -000 ---0 ---u uuuu uuuu ---uuuu uuuu uuu- ---u--u -uuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu 00-0 1uuu -000 ---0 ---u uuuu uuuu ---uuuu uuuu uuu- ---u--u -uuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu RES Reset (HALT) 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu 00-0 1uuu -000 ---0 ---u uuuu uuuu ---uuuu uuuu uuu- ---u--u -uuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu WDT Time-out (HALT) 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uu-u uuuu -uuu ---u ---u uuuu uuuu ---uuuu uuuu uuu- ---u--u -uuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
u means unchanged x means unknown - means undefined
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Input/Output Ports There are 23 bidirectional input/output lines in the microcontroller, labeled from PA to PC, which are mapped to the data memory of [12H], [14H], and [16H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A, [m] (m=12H,14H or 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, and 17H. Bit 7 which is mapped to location [17H] is always written as 1. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The wake-up capability of port A is determined by mask option. There is a pull-high option available for all I/O lines. Once the pull-high option is selected, all I/O lines have pull-high resistors. Otherwise, the pull-high resistors are absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. By some different mask options, there are 3 shared pins (PC.4, PC.5, and PC.6) in PC. They can be normal I/O pins or for special functions. The PC.4 is the external clock source of timer/event counter TMR0 if TMR0 is set to external clock mode, and the PC.5 is the external clock source of timer/event counter TMR1 if TMR1 is set to external clock mode. PC6 is pin-shared with XIN. The XIN and XOUT can be connected to a 32kHz crystal as the clock source of the timer counter TMR3 if the mask option is set to enable 32kHz (RTC) crystal.
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D W r ite I/O
D CK S
Q
V V
DD
Q
DD
W eak P u ll- u p M a s k O p tio n
Q CK S
PA0~PA7 PB0~PB7 PC 0~PC 6
Q
M U X
R e a d I/O S y s te m W a k e - U p ( P A o n ly ) M a s k O p tio n
Input/Output Ports
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Audio Output and Volume Control - DAL, DAH, VOL The HT86XXX provides one 12-bit current type DAC device for driving external 8W speaker through an external NPN transistor. The programmer must write the voice data to register DAL (27H) and DAH (28H). The 12-bit audio output will be written to the higher nibble of DAL and the whole byte of DAH, and the DAL3~0 is always read as 0H. There are 8 scales of volume controllable level that are provided for the current type DAC output. The programmer can change the volume by only writing the volume control data to the higher-nibble of the VOL (29H), and the lower-nibble of VOL (29H) is always read as 0H. Voice Control Register - VOICEC (26H) The voice control register controls the voice ROM circuit and DAC circuit, selects voice ROM latch counter, and controls 32kHz crystal to start in speed-up mode or not. If the DAC circuit is not enabled, any DAH/DAL output is invalid. Writing a 1 to DAC bit is to enable DAC circuit, and writing a 0 to DAC bit is to disable DAC circuit. If the voice ROM circuit is not enabled, then voice ROM data cannot be accessed at all. Writing a 1 to VROMC bit is to enable the voice ROM circuit, and writing a 0 to VROMC bit is to disable the voice ROM circuit. The bit 4 (LATCHC) is to determine what voice ROM address latch counter will be adopted as voice ROM address latch counter. The bit 7 (FAST) is to determine how to activate 32kHz crystal of TMR3s clock source. Label 3/4 Bits 0 Function Unused bit, read as 0 Enable/disable DAC circuit (0= disable DAC circuit; 1= enable DAC circuit) The DAC circuit is not affected by the HALT instruction. The s of t w ar e c o n t r ol s b i t D A C (VoiceC.1) whether to enable/disable. Enable/disable voice ROM circuit (0= disable voice ROM circuit; 1= enable voice ROM circuit) Unused bit, read as 0 Select voice ROM counter (0= voice ROM address latch 0; 1= voice ROM address latch 1) Enable/disable speed-up 32kHz crystal. Default to 0. (0= speed-up 32kHz crystal; 1= non-speed-up 32kHz crystal) Voice ROM Data Address Latch Counter LATCH0H(18H)/LATCH0M(19H)/LATCH0L(1AH), LATCH1H(1BH)/LATCH1M(1CH)/LATCH1L(1DH) and voice ROM data register(2AH) The voice ROM data address latch counter is the handshaking between the microcontroller and voice ROM, where the voice codes are stored. One 8-bit of voice ROM data will be addressed by setting 24-bit address latch counter LATCH0H/LATCH0M/LATCH0L or LATCH1H/LATCH1M/LATCH1L. After the 8-bit voice ROM data is addressed, a few instruction cycles (4ms at least) will be cost to latch the voice ROM data, then the microcontroller can read the voice data from LATCHD(2AH). Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0 set clr mov mov mov mov mov mov call mov [26H].2 [26H].4 A, 07H A, 00H A, 00H Delay Time A, LATCHD ; Enable voice ROM circuit ; Select voice ROM address ; latch counter 0 ; ; ; ; Delay a short period of time ; Get voice data at 000007H
LATCH0L, A ; Set LATCH0L to 07H LATCH0M, A ; Set LATCH0M to 00H LATCH0H, A ; Set LATCH0H to 00H
DAC
1
VROMC 3/4 LATCHC 3/4 FAST
2 3 4
5, 6 Unused bit, read as 0 7
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HT86XXX
Mask Option Mask Option PA Wake-up Watchdog Timer (WDT) Description Enable/disable PA wake-up function Enable/disable WDT function One or two CLR instruction WDT clock source is from WDTOSC or T1 External INT is triggered on falling edge only, or is triggered on falling and rising edge. Timer3s clock source is from T1, or is from the external 32kHz crystal which is connected to XIN and XOUT.
External INT Trigger Edge Timer 3 Clock Source
External Timer 0/1 Clock Source Enable/disable external timer of timer 0 and timer 1, share with PC4 and PC5. PA Pull-high PB Pull-high PC Pull-high fOSC - ROSC Table (VDD=3V) fOSC 4MHz10% 6MHz10% 8MHz10% ROSC 100kW 75kW 62kW Enable/disable PA pull-high Enable/disable PB pull-high Enable/disable PC pull-high
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Application Circuits
V
DD
10W 0 .1 m F 47mF
VDDA
OSC2 OSC1
V
DD
100kW ~62kW VDD PA0~PA7 PB0~PB7 RES PC0~PC 6
0 .1 m F
100mF
V
DD
100kW
SPK (8 W /1 6 W ) 8050 R2
0 .1 m F
V
DD
AUD VSS IN T VSSA
R1
H T86XXX
N o te : R 1 > R 2
V
DD
10W 0 .1 m F 47mF
VDDA
OSC2 OSC1
4M H z~8M H z
V
DD
PA0~PA7 VDD PB0~PB7 PC0~PC 6 RES
100mF
100kW
CE 5 1 OUTN VDD 8
SPK (8 W /1 6 W )
AUD
A u d io In
V
DD
0 .1 m F
V
0 .1 m F 2 3
DD
A u d io In VREF
H T82V733
OUTP
47mF 4
VSS IN T VSSA
10mF
NC
6
7
H T86XXX
Rev. 1.70
32
May 6, 2004
HT86XXX
Package Information
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
Rev. 1.70
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HT86XXX
32-pin SOP (450mil) Outline Dimensions
32 A
17 B
1
16
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 543 440 14 3/4 100 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 557 450 20 817 112 3/4 3/4 38 12 10
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HT86XXX
100-pin QFP (1420) Outline Dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
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HT86XXX
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
SOP 32W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 1000.1 13.0+0.5 -0.2 2.00.5 32.8+0.3 -0.2 38.2+0.2
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HT86XXX
Carrier Tape Dimensions
D
E F
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
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HT86XXX
P0 D
E F W C B0
P1
t
D1
P K2 A0
K1
SOP 32W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.0+0.3 -0.1 16.00.1 1.750.1 14.20.1 1.55+0.1 2.0+0.25 4.00.1 2.00.1 14.70.1 20.90.1 3.00.1 3.40.1 0.350.05 25.5
Rev. 1.70
38
May 6, 2004
HT86XXX
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.70
43
May 6, 2004

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